This application claims the benefit of Japanese Patent Application No. 1998-309237, filed on Oct. 29, 1998, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a method of forming silicon oxide layer and method of manufacturing thin film transistor (TFT) thereby, and more particularly, to a method of forming silicon oxide layer preferably used as a gate insulator and an interspacing insulator.
2. Discussion of the Related Art
A liquid crystal display device (LCD) has been used widely to be minimized, lightened, and thinned, for example, an active matrix LCD of a twisted nematic (TN) mode has been known as a display device which has a low driving voltage, a small electric power consumption, a high contrast, and a high image quality.
In the active matrix LCD, a pair of substrates are opposing each other by interposing a liquid crystal layer, and one substrate between them is an active matrix substrate which has a switching element driving a pixel in each pixel.
FIG. 13 is showing a TFT which is a switching element of the active matrix substrate, and more particularly, showing a top-gate TFT. As shown in the figure, in the TFT 50, a semiconductive layer 52 is formed in an island type on a transparent substrate 51, and an interspacing insulator 53 is formed to cover the semiconductive layer 52 on the transparent substrate 51. In addition, contact holes 54, 55 are formed in the interspacing insulator 53, and source and drain electrodes 56, 57 are formed to connect the semiconductive layer 52 through the contact holes 54, 55 respectively.
Further, a passivation layer 58 is formed on the interspacing insulator 53 to cover the source and drain electrodes 56, 57, a contact hole 59 is formed in the passivation layer 58, and a pixel electrode 60 is formed to connect to the drain electrode 57 through the contact hole 59.
The semiconductive layer 52 comprises a source region 61, a drain region 62, and a channel region 63 between the source and drain regions 61, 62. And, the source electrode 56 is connected to the source region 61 and the drain electrode 57 is connected to the drain region 62. A gate insulator 64 is formed on the channel region 63 of the semiconductive layer 52, and a gate electrode 65 is formed on the gate insulator 64.
As to the TFT 50 shown in the FIG. 13, generally, the semiconductive layer 52 includes amorphous silicon (a-Si) or poly silicon (Poly-Si), the source, drain, and gate electrodes 56, 57, 65 include conductive metals, and the pixel electrode 60 is formed as a transparent conductive layer of indium tin oxide (ITO).
The insulating layer such as the gate insulator 64, the interspacing insulator 53, and the like includes silicon oxide (SiO2) layer. In the TFT 50, the electric charge induced on the channel region 63 is controlled by the electric field when a voltage is applied to the gate electrode 65, which make the current flowing between the source and drain electrodes to be on or off. And then the TFT functions as a switching element.
As described above, while it is necessary an insulating layer such as the gate insulator, the interspacing insulator, and the like to the TFT, the capabilities required to the gate insulator and interspacing insulator are different from each other respectively.
The gate insulator is the best important element which affects on the electric characteristic of the TFT, for example a threshold voltage, and so on. Hence, as the material for the gate insulator, it is required that the characteristic is stable and the insulating pressure is good although the thickness of the insulating layer is thin.
On the other hand, the interspacing insulator maintains the insulation between the conductive layers by interposing between two different conductive layers as being between the gate and source electrodes, or between the gate and drain electrodes.
As shown in the FIG. 13, however, the interspacing insulator is formed according to the step of the gate electrode or semiconductive layer, so that if the step coverage of the interspacing insulator is bad, there is a problem that the insulating pressure at the steps is lowered. Therefore, it is required the interspacing insulator which has a good step coverage and particularly has a high insulating pressure at the steps.
To form the silicon oxide layer used in these insulating layers, it has been known to employ the plasma CVD using tetraethlyorthosilicate (TEOS) as the material gas. Since the silicon oxide layer of TEOS group has a good step coverage, it is suitable for the interspacing insulator. However, there are problems that the formation speed of the layer is slow, the insulating pressure is low, and so on, further it could not be used as the gate insulator. Moreover, TEOS is in a liquid state at room temperature, so that it is difficult to employ the CVD using the TEOS after vaporizing this, and there is also the matter of high costs.
In addition, to form the silicon oxide layer used in these insulating layers, it has been known to employ a plasma CVD using the mixing gas of monosilane (SiH4) and nitrous oxide (N2O) as the material gas. Regarding this silicon oxide layer, because the step coverage is too bad and there is a concern of generating cracks from the steps into the layer, it could be used to the gate insulator, but it is not suitable for the interspacing insulator.
As described above, as to the insulating layer in the TFT, since the capabilities required according to the uses such as the gate insulator, the interspacing insulator, and the like differ respectively, it is necessary to use the material of the insulating layer according to the uses. However in this case, because of the process limitation according to the material gas, the degree of freedom in the process is lowered and it becomes a bad manufacturing process with a small productivity.
Therefore, although the silicon oxide layer is formed by the plasma CVD using same material gas, it could be used without regard to the uses such as the gate insulator, the interspacing insulator, and the like, and then it is required for rationalizing of the manufacturing process.
Accordingly, the present invention is directed to a method of forming silicon oxide layer that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method of forming a silicon oxide layer being used as a gate insulator and an interspacing insulator. The silicon oxide layer has good characteristics such as the insulating pressure or the step coverage, improving the yield of the TFT, having no problems of treatment or cost. And the other object of the present invention is to provide a method of manufacturing a TFT with using the silicon oxide layer.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method of forming a silicon oxide layer comprises the steps of:
providing two frequency excitation plasma CVD device which comprises a first high frequency power supply, a high frequency electrode connected to the a first high frequency power supply, a matching box toward the high frequency electrode having a matching circuit obtaining a matching of impedance between the first high frequency power supply and high frequency electrode; a second high frequency power supply, a susceptor electrode connected to the second high frequency power supply opposing the high frequency electrode and supporting a substrate, and a matching box toward the susceptor electrode having a matching circuit obtaining a matching of impedance between the second high frequency power supply and susceptor electrode, wherein one electrode among at lease two electrodes which constitute at least tuning condenser in the matching circuit of the matching box toward the high frequency electrode is the high frequency electrode;
placing the substrate on the susceptor electrode;
applying high frequency electric power on the high frequency electrode and the susceptor electrode respectively; and
forming a silicon oxide layer on the substrate by generating plasma with using a reaction gas in which a flow ratio of the mixing gas of monosilane and nitrous oxide is 10 to 50%.
In the conventional plasma CVD device, a susceptor placing a substrate was provided in a chamber, an electrode was formed corresponding thereto, a high frequency electric power is applied to the electrode, and plasma was generated by leading a reaction gas.
As to the above constitution, the present inventors had already filed a Patent Application of two frequency excitation plasma CVD device that the susceptor placing the substrate would be an electrode and then bias electric power could be applied to the substrate.
Among the two matching box insulted into between the first high frequency power supply and high frequency electrode, and the second high frequency power supply and susceptor electrode, if one side electrode of the tuning condenser in the matching circuit of the matching box toward the high frequency electrode is used as the high frequency electrode, it is possible to obtain a plasma CVD device having the advantages that the electric power decreases, the electric power consumption efficiency is high, the layer formation speed is rapid, and then it could obtain the layer with a good quality.
Therefore, the present inventors use the two frequency excitation plasma CVD device with the matching box, the material gas of which main reaction gases are monosilane gas and nitrous oxide gas widely used in forming a silicon oxide layer. And the formation of the silicon oxide layer is performed with changing the formation condition such as the flow ratio of gases, etc.
As the result of, in the two frequency excitation plasma CVD device, if it use the reaction gas in which the flow ratio of the mixing gas of monosilane and nitrous oxide is 10 to 50%, it could obtain the silicon oxide layer as good as the silicon oxide layer of the TEOS group, although the N2O/SiH4 based silicon oxide layer is a bad step coverage compared with the conventional silicon oxide layer of the TEOS group.
As to the reaction gas, the flow ratio of nitrous oxide to monosilane is preferably 10 or more.
If the flow ratio of nitrous oxide to monosilane is 10 or more, the stoichiometric structure of the silicon oxide layer is proved by the refractivity experiment and a silicon oxide layer having a sufficiently high formation speed is obtained. From the above, the step coverage is improved, and when the flow ratio is 10 or more, the insulating pressure is enhanced, also.
As to the reaction gas of which main gases are 10 to 50% of nitrous oxide and monosilane, other gas among the reaction gas includes a gas selected from the group consisting of helium, hydrogen, xenon, oxygen, argon, nitrogen and a mixing thereof.
These gases affect secondarily to the reaction of the main reaction gas. For example, helium, hydrogen, and xenon accelerate the reaction at the point that ionization energy is high, and have an effect of improving the stability of the plasma. Oxygen supplies the quantity of oxygen ion on the formation of the layer. Argon, nitrogen accelerate the kinetic energy of the various ions generated by the main reaction gas, and then accelerate the reaction.
As to the two frequency excitation plasma CVD device, a frequency of high frequency electric power applied to the high frequency electrode is in range of 13.56 MHz to 100 MHz. If the frequency of high frequency electric power applied to the high frequency electrode is below 13.56 MHz, the potential difference between the high frequency electrode and the excited plasma is higher, the high frequency electrode is easy to be damaged and then it is not practical.
Further, when the frequency of high frequency electric power applied to the high frequency electrode is over 100 MHz, the manufacturing of the power supply is difficult, and the output is unstable, and then it is not practical.
On the other hand, if a frequency of high frequency electric power applied to the susceptor electrode is below 50 kHz, the susceptor electrode is easy to be damaged like the high frequency electrode. If the frequency is over 1.6 MHz, it is difficult to discharge between the high frequency electrode the susceptor electrode, the electric power consumption efficiency decreased, and then it is not practical.
The present invention provides the silicon oxide layer having a high formation speed of the layer and a good quality. However, in the matching box toward the high frequency electrode of the two frequency excitation plasma CVD device, a feed wire providing the high frequency electrode with the high frequency electric power in the first high frequency supply through the matching circuit is not parallel with a side wall of a housing having a conductive material in the matching box.
In the two frequency excitation plasma CVD device, the high frequency current on supplying power flows through the high frequency power supply, coaxial cable, matching circuit, feed wire, high frequency electrode, plasma space, susceptor electrode, side wall of chamber, and housing side wall of matching box.
However, if the side wall of the housing is not parallel with the feed wire, the flowing directions of the going and returning currents are not parallel with each other, and it prevents the mutual inductance from increasing. Therefore, the electric power consumption efficiency increases, and it improves the formation speed of the layer and the quality of the layer.
The present method of manufacturing a thin film transistor comprises forming a gate insulator and an interspacing insulator of the thin film transistor with the silicon oxide layer obtained by the method of forming the silicon oxide layer as described above.
From the method of forming the silicon oxide layer, it improves the electric power consumption efficiency of the plasma CVD device and the formation speed of the layer. Further, the formation speed of the layer on a small substrate increases by applying the bias electric power on the substrate, and then the step coverage becomes preferable.
Hence, the N2O/SiH4 based silicon oxide layer is able to be used as the interspacing insulator as the conventional TEOS based silicon oxide layer is. Furthermore, since the improvement of the layer quality, particularly, the improvement of the insulating pressure is obtained, it is possible to apply to the gate insulator.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.